Description
The real H100 SXM capture supplies a sourced hardware envelope, but the frozen topology accepts only PCIe and NVL72 shapes. Add an additive HGX declaration without changing existing products.
Acceptance Criteria
- #1 An hgx pool is declarable with eight H100 SXM GPUs per node
- #2 Each HGX node has four NVSwitches and eighteen NVLinks per GPU with an intra-node switch/link map
- #3 The h100_sxm_80gb catalogue row is sourced from the capture or pinned vendor documentation; unsupported values stay nullable
- #4 Existing pcie and nvl72 topology, identity and physics output is byte-identical under fixed process-edge inputs
- #5 New load-time rejections are tested through the real blueprint loader
- #6 The HGX declaration, identities, capabilities and limitations are documented
Definition of Done
- #1 just check (fmt-check, lint, gen-check, env-check, docs-check, test, race, hygiene, ui-check, compose-check, helm-test, lab-check, signal-fidelity)
- #2 just gen (only if a blueprint field, construct/workload config struct, or a skill under plugins/synthkit/skills/ changed)
- #3 just dump — inventory diffed against signals/
Implementation Plan
Implement frozen additive HGX rev5.1 declarations, exact pinned endpoint projection and node-local identities; accepted SXM thermal row and explicit sourced per-GPU usable framebuffer; preserve old PCIe/NVL72 output byte-for-byte through real loader under fixed inputs; validate new rejection/capability/fault paths, gen/dump, own just check, root batch review and landing CI.
Retry2: relocate the existing full real-loader cross-revision compatibility proof to one specifically owned integration test; preserve all assertions, both profiles and fixed input/output comparisons. Keep all HGX branch tests in fixture/blueprint packages, compare output to the preserved prior artifact, complete guard-mutation negative controls, then gen, inventory and exact committed full check.
Implementation Notes
loop48 R0: admitted HGX seam design under Rob 2026-10-03 additive-only decision; implementation waits for independent challenge, freeze and accepted DCGM rev3.
loop48: root froze additive HGX rev5.1 after second independent challenge, contract codex/packets-2026-10-03-loop48/contracts/fixture-design-rev5.md sha256 5d1cf79707e7d7b5010740b0128a3f08e8ac2df0652a7c17167473110a52070f, UTC 2026-10-03T14:43:44Z. Complete static vendor topology proved; CSV full-map fidelity comparison required, CRC-only HGX diagnostic policy explicit and not a vendor claim. Remaining proof belongs to implementation; no compatibility/consumer completion inferred.
loop48 implementation1 candidate0d55bccbe5542c0b4f0006f21dd6fa59b0bb6e78: focused source projection, real loader, full fixed-input old/candidate comparison (48223638 bytes, matching cec2ab6b5b5afc4f4f65d6d441fdb724ddb63320901377592a19be485a0dbcf1), gen and inventories passed. Full check failed at race timeout in the exhaustive compatibility test; later legs unobserved. Implementation1 settled, infra0, review-repair0. Retry2 will preserve full comparisons/assertions in the existing integration-test tier, retain fast HGX/rejection/fault tests in race-covered packages, and complete falsifiable negative controls without weakening guards or timeouts; no race-recipe change.
loop48: implementations1-2, infra0, review-repair0; landed89f4c81fe2368df95f695c5d0a7868d384b9235c, ci37140297969 all10 jobs success, exact root readback verified. CodeRabbit0 findings/full22-file batch coverage. Compatibility48223638bytes SHAcec2ab6b5b5afc4f4f65d6d441fdb724ddb63320901377592a19be485a0dbcf1. Nonblocking proof gap: an extra direct-domain-node-parent mutant survived a reachability assertion; candidate parent is correct and this extra control is not counted as passing.
Final Summary
Delivered additive sourced HGX topology and H100 SXM envelope, exact pinned 144-edge map, strict real-loader admission and unchanged prior PCIe/NVL72 output. Root gen/dump and neutral check passed at 89f4c81fe2368df95f695c5d0a7868d384b9235c; inventory unchanged at 327 patterns. Exhaustive compatibility runs in the existing plain integration tier; fast HGX tests remain race-covered. All eight external optional-lane rows remain BLOCKED_EXTERNAL, not passes.